1. Field of the Invention
The present invention relates to a semiconductor structure and a method for manufacturing the same, especially to a super junction for semiconductor device and a method for manufacturing the same.
2. Description of Related Art
Since the first introduction by Dr. Chen in 1991, super junction devices are under substantive research for improved performance.
For example, U.S. Pat. No. 6,608,350 was disclosed with a trench type super junction device. FIG. 1 shows the sectional view of the trench type super junction device in U.S. Pat. No. 6,608,350. The trench type super junction MOS device comprises a substrate 81, an N type epitaxial layer 82, a plurality of parallel trenches 83, P type layer 84 on sidewall of each trench 83, P base 93 on the N type epitaxial layer 82, gate oxide layer 87 and gate 88 between two adjacent trenches 83 and atop the N type epitaxial layer 82, source 89 and source electrode 91 atop the P base 93, and dielectric layer (not labeled) in the P type layer 84. In conductive mode, a bias is applied to the gate 88 and the source 89 is grounded. A channel is formed between the P base 93 and the gate oxide layer 87 and current is generated when bias is applied to drain of this device. The P type layer 84 on sidewall of each trench 83 can provide lower on resistance RDSON. In conventional MOS device, the resistivity of the N type epitaxial layer 82 should be lower (the doping concentration should be higher) to reduce on resistance RDSON. However, the voltage tolerance is affected when the doping concentration of the N type epitaxial layer 82 increases.
The above-mentioned super junction structure can provide the advantage of both high voltage tolerance and lower on resistance. However, it is difficult to form trench with high aspect ratio on N type epitaxial layer 82. Therefore, a novel super junction structure for semiconductor device and method for the same are desirable.
There are several methods using repeated epitaxial growth and implant P-column steps to form superjunction MOSFET according to charge balance concept theory. Unfortunately, this process is very sensitive to process tolerance (<1%), which is not manufacturable for existing tool capability in epitaxial reactors and ion implanters. Once ion implant and epitaxial growth are completed, there is no way to do fine tuning.
The present invention is proposed to form a second implant step for fine tuning current dose or counter dose to obtain much better charge balance. 4-point SRP and P-column cross dimension (CD) data are required after ion implantation to determine how much the concentration and charge are introduced. Compared it with the target, the balance concentration and charge can be calculated. Then, a modified dose of second implant will be implanted to meet target. The extra center and peripheral areas are for the second implant to do better charge balance. In this way, for example, breakdown voltage (BV) will be in the range of 600V-700V instead of 500V-600V in mass production (MP).